Introduction to memory
It cancels the time interval between the two storage cycles of the motherboard and the memory, and transmits data every 2 clock pulse cycles, which greatly shortens the access time. Increase the access speed by 30% to 60ns. EDO memory is mainly used for 72-line SIMM memory sticks and PCI display cards using EDO memory chips. This kind of memory is popular in 486 and early Pentium computer systems. It has 72 lines and 168 lines. It adopts 5V working voltage and 32 bit bus width. It must be used in pairs of two or four. It can be used for Intel 430FX/430VX or even Intel 430FX/430VX. 430TX chipset on the motherboard. It has also been eliminated and can only be seen on some old planes.
How it works
There is a great way to read the next data after reading EDO DRAM and older FPM DRAM. Difference. EDO DRAM can perform the next column address strobe while outputting data. We still use the following EDO reading timing diagram to understand the process of EDO DRAM reading data:
1, RAS ends the last time After the read operation, enter the pre-charged state. After receiving the request to read the data, the row address is first transmitted to the address pin through the address bus. During this period, the CAS is still in the pre-charged state. 2. The /RAS pin is activated, and the column address starts to pass through the row address strobe circuit and the row address decoder to select the row address. At this same time, the tRAC cycle starts because the read operation /WE pin has not been activated. , So the memory knows that it is doing a read operation rather than a write operation.
3. While the CAS is still precharging, the column address is sent to the column address strobe circuit to select the appropriate address. When /CAS is activated, the tCAC cycle starts, and when tCAC ends At this time, the data that needs to be read will be transferred to the data bus through the data pin.
4. From the beginning of outputting the first set of data, we can understand the difference between EDO and FPM: before the end of the tCAC cycle, CAS is deactivated and precharged, and the second The group column address transmission and strobe also start immediately, before the first data is output, the tCAC cycle of the next group of data starts-obviously this saves time further. Just before the second set of data is output, CAS is again deactivated to prepare for the third set of data transmission column addresses...
5. Such a design makes the performance of EDO memory higher than that of FPM About 20-40%.
6. Just because EDO is faster than FPM, it can run at a higher bus frequency. So many EDO RAMs can run at 66MHz, and they are generally labeled 5-2-2-2.
Memory picture
1, 72-line EDO memory
2, 168-line EDO memory
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