Basic information
Since Intel Corporation in the United States designed and manufactured 4-bit microprocessor chips in 1971, in more than 20 years, CPUs have evolved from Intel4004, 80286, 80386, 80486 to Pentium And PentiumⅡ, the number has developed from 4, 8, 16 and 32 bits to 64 bits; the main frequency has increased from a few megabytes to more than 3GHz today; the number of transistors integrated in the CPU chip has jumped from 2,000 to more than 5 million; semiconductors The scale of manufacturing technology has reached ULSI from SSI, MSI, LSI, and VLSI. The input/output (I/O) pins of the package have gradually increased from dozens to hundreds, and may reach 2,000 at the beginning of the next century. All this is really an earth-shaking change.
When it comes to the packaging of CPUs and other large-scale integrated circuits, not many people know it. The so-called package refers to the housing used to install the semiconductor integrated circuit chip. It not only plays the role of placing, fixing, sealing, protecting the chip and enhancing the electrothermal performance, but also a bridge between the internal world of the chip and the external circuit. The contacts on the chip use wires. It is connected to the pins of the package shell, and these pins are connected to other devices through wires on the printed board. Therefore, packaging plays an important role for both CPU and other LSI integrated circuits. The emergence of a new generation of CPUs is often accompanied by the use of new packaging forms.
Chip packaging technology has undergone several generations of changes, from DIP, QFP, PGA, BGA to CSP to MCM, the technical indicators are more advanced from generation to generation, including the ratio of chip area to package area. The closer it is to 1, the higher the applicable frequency, the better the temperature resistance, the increase of the number of pins, the reduction of the pin spacing, the reduction of weight, the improvement of reliability, and the more convenient to use.
Detailed explanation of common packages
DIP package
In the 1970s, the popular dual in-line package, referred to as DIP (Dual In-line Package). The DIP package structure has the following characteristics:
1. Suitable for PCB through hole mounting
2. It is easier to wire the PCB than the TO type package
3. Convenient operation< /p>
DIP package structure has multilayer ceramic dual in-line DIP, single-layer ceramic dual in-line DIP, lead frame DIP (including glass ceramic sealing type, plastic encapsulation structure, low ceramic Melt glass package type).
An important indicator to measure whether a chip packaging technology is advanced or not is the ratio of chip area to packaging area. The closer this ratio is to 1, the better. Take the CPU with 40 I/O pins plastic encapsulated dual in-line package (PDIP) as an example, its chip area/package area=3×3/15.24×50=1: 86, which is far away from 1. . It is not difficult to see that this package size is much larger than the chip, indicating that the packaging efficiency is very low, taking up a lot of effective mounting area.
Intel's CPUs such as 8086 and 80286 during this period all adopted PDIP package.
Chip carrier packaging
In the 1980s, chip carrier packaging appeared, including ceramic leadless chip carrier LCCC (Leadless Ceramic Chip Carrier) and plastic leaded chip carrier PLCC (Plastic Leaded Chip Carrier). Carrier), SOP (Small Outline Package), and PQFP (Plastic Quad Flat Package).
Take 0.5mm welding zone center distance, 208 I/O pins QFP packaged CPU as an example, the outline size is 28×28mm, the chip size is 10×10mm, then the chip area/package area=10 ×10/28×28=1:7.8, it can be seen that the package size of QFP is greatly reduced compared with DIP. The characteristics of QFP are:
1. It is suitable for installing and wiring on PCB with SMT surface mounting technology
2. The package size is small, the parasitic parameters are reduced, and it is suitable for high-frequency applications
p>3. Convenient operation
4. High reliability
During this period, Intel’s CPUs, such as Intel 80386, used plastic quad flat package PQFP.
BGA package
In the 1990s, with the advancement of integration technology, the improvement of equipment and the use of deep sub-micron technology, LSI, VLSI, ULSI appeared one after another, and the integration of silicon single chip continued Increased requirements for integrated circuit packaging have become more stringent, the number of I/O pins has increased dramatically, and power consumption has also increased. In order to meet the needs of development, on the basis of the original packaging varieties, a new variety has been added-Ball Grid Array Package, referred to as BGA (Ball Grid Array Package).
As soon as BGA appeared, it became the best choice for high-density, high-performance, multi-function, and high-I/O pin packaging for VLSI chips such as CPUs and north-south bridges. Its characteristics are:
1. Although the number of I/O pins has increased, the pin spacing is much larger than QFP, which improves the assembly yield;
2. Although its function Consumption increases, but BGA can be welded by the controllable collapse chip method, referred to as C4 welding, which can improve its electric heating performance;
3. The thickness is reduced by more than 1/2 compared with QFP, and the weight is reduced by more than 3/4 ;
4. The parasitic parameters are reduced, the signal transmission delay is small, and the frequency of use is greatly improved;
5. The assembly can be coplanar welding, and the reliability is high;
6. BGA package is still the same as QFP and PGA, occupying too much substrate area.
Intel Corporation has a high level of integration (more than 3 million transistors in a single chip) and high power consumption CPU chips, such as Pentium, Pentium Pro, and Pentium Ⅱ, which are packaged in ceramic pin grid arrays. CPGA and ceramic ball grid array package CBGA, and install a miniature exhaust fan on the shell to dissipate heat, so as to achieve the stable and reliable operation of the circuit.
New packaging technology
BGA packaging is more advanced than QFP and better than PGA, but its chip area/package area ratio is still very low.
Tessera has made improvements on the basis of BGA and developed another packaging technology called μBGA. According to the 0.5mm pad center distance, the chip area/package area ratio is 1:4. BGA has taken a big step forward.
In September 1994, Japan's Mitsubishi Electric developed a package structure with chip area/package area=1:1.1, and its package outline size is only slightly larger than that of the bare chip. In other words, how big a single IC chip is, and how big the package size is, thus a new packaging form was born, named Chip Size Package, or CSP (Chip Size Package or Chip Scale Package) for short. The CSP package has the following features:
1. It meets the ever-increasing need of LSI chip lead pins
2. It solves the problem that the IC bare chip cannot be tested for AC parameters and aging screening< /p>
3. The package area is reduced to 1/4 to 1/10 of the BGA, and the delay time is reduced to a very short time.
When a single chip cannot achieve the integration of multiple chips for a while , Can high-integration, high-performance, high-reliability CSP chips (using LSI or IC) and application-specific integrated circuit chips (ASIC) be assembled on high-density multilayer interconnection substrates with surface mount technology (SMT) into a variety of Electronic components, subsystems or systems. From this idea, a multi-chip component MCM (Multi Chip Model) was produced. It will have a major impact on modern computers, automation, communications and other fields. The features of MCM are:
1. The package delay time is reduced, which is easy to achieve high-speed components;
2. The package size and weight of the whole machine/component are reduced, and the general volume is reduced by 1/ 4. The weight is reduced by 1/3;
3. The reliability is greatly improved.
With the advancement of LSI design technology and process and the use of deep sub-micron technology and miniaturization to reduce chip size, people have produced multiple LSI chips assembled in a precision multilayer wiring housing Form the idea of MCM products. Another idea was further produced: integrating the circuits of multiple chips on a large wafer, which in turn led to a change in packaging from a single chip level to a wafer level package, which led to the system level chip SOC (System On Chip) and PCOC (PC On Chip).
With the advancement of CPUs and other ULSI circuits, the packaging forms of integrated circuits will also develop correspondingly, and the advancement of packaging forms will in turn promote the development of chip technology.
Packaging development process
Structural aspects: TO－>DIP－>LCC－>QFP－>BGA －>CSP－>WLP;
Material: metal, ceramic -> ceramics, plastic -> plastic;
Pin shape: long lead in-line -> short lead or no lead mounting -> spherical convex Point;
Assembly method: through-hole insert->surface assembly-> direct installation.
DIP--Double In-line Package--Dual in-line package. One of the plug-in packages, the pins are drawn from both sides of the package, and the package materials are plastic and ceramic. DIP is the most popular plug-in package, and its applications include standard logic ICs, memory LSIs, and microcomputer circuits.
PLCC--Plastic Leaded Chip Carrier--PLCC package, the shape is square, 32-pin package, there are pins on all sides, and the size is much smaller than DIP package. The PLCC package is suitable for installing and wiring on the PCB with SMT surface mounting technology, and has the advantages of small size and high reliability.
PQFP--Plastic Quad Flat Package--PQFP package has a small distance between the pins of the chip, and the pins are very thin. Generally, large-scale or very large-scale integrated circuits use this type of package, and its pins The numbers are generally above 100.
SOP--Small Outline Package--From 1968 to 1969, the Philippine Company developed a small outline package (SOP). Later, SOJ (J-pin small outline package), TSOP (thin small outline package), VSOP (very small outline package), SSOP (reduced SOP), TSSOP (thin reduced SOP), and SOT (small outline package) were gradually derived. Shape transistor), SOIC (Small Outline Integrated Circuit), etc.
Various package types
1. BGA (ball grid array)
Ball contact array, one of surface mount packages. On the back of the printed circuit board, spherical bumps are produced in the display mode to replace the pins, and the LSI chip is assembled on the front side of the printed circuit board, and then sealed by molding resin or potting. Also called bump display carrier (PAC). Pins can exceed 200, which is a package for multi-pin LSI.
The package body can also be made smaller than QFP (Quad Flat Package). For example, a 360-pin BGA with a pin center distance of 1.5mm is only 31mm square; while a 304-pin QFP with a pin center distance of 0.5mm is 40mm square. And BGA does not have to worry about pin deformation like QFP. This package was developed by Motorola Corporation of the United States. It was first adopted in portable phones and other devices, and may be popularized in personal computers in the United States in the future. Initially, the BGA pin (bump) center distance was 1.5mm, and the number of pins was 225. Some LSI manufacturers are also developing 500-pin BGAs. The problem with BGA is the visual inspection after reflow soldering. It is not clear whether there is an effective visual inspection method. Some believe that due to the large center distance of welding, the connection can be regarded as stable and can only be processed through functional inspection. The American Motorola Company calls the package sealed with molded resin OMPAC, and the package sealed by the potting method is called GPAC (see OMPAC and GPAC).
2. BQFP (quad flat package with bumper)
Quad flat package with bumper. One of the QFP packages, bumps (buffer pads) are provided at the four corners of the package body to prevent bending and deformation of the pins during transportation. American semiconductor manufacturers mainly use this package in circuits such as microprocessors and ASICs. The pin center distance is 0.635mm, and the number of pins is about 84 to 196 (see QFP).
3. Butt joint pin grid array (butt joint pin grid array)
Another name for surface mount PGA (see surface mount PGA).
4. C－(ceramic)
The symbol of ceramic package. For example, CDIP stands for ceramic DIP. It is a mark that is often used in practice.
5. Cerdip
Use glass-sealed ceramic dual-in-line package for ECL RAM, DSP (digital signal processor) and other circuits. Cerdip with glass window is used for ultraviolet erasable EPROM and microcomputer circuit with EPROM inside. The pin center distance is 2.54mm, and the number of pins is from 8 to 42. In Japan, this package is expressed as DIP-G (G means glass seal).
6. Cerquad
One of the surface mount packages, the ceramic QFP sealed under the seal, is used to package logic LSI circuits such as DSP. Cerquad with windows is used to encapsulate EPROM circuits. The heat dissipation is better than that of plastic QFP, and it can tolerate 1.5~2W power under natural air cooling conditions. But the packaging cost is 3 to 5 times higher than that of plastic QFP. The pin center distance has a variety of specifications such as 1.27mm. 0.8mm. 0.65mm. 0.5mm. 0.4mm. The number of pins ranges from 32 to 368.
7. CLCC (ceramic leaded chip carrier)
Ceramic leaded chip carrier, one of the surface mount packages. The pins are led out from the four sides of the package. T-shaped. It is used to encapsulate the ultraviolet erasable EPROM and the microcomputer circuit with EPROM with windows. This package is also called QFJ. QFJ-G (see QFJ). 8. COB (chip on board) chip packaging is one of the bare chip mounting technologies. The semiconductor chip is handed over and mounted on the printed circuit board. The electrical connection between the chip and the substrate is realized by wire stitching. The electrical connection between the chip and the substrate The connection is made by wire stitching and covered with resin to ensure reliability. Although COB is the simplest bare chip mounting technology, its packaging density is far inferior to TAB and flip-chip bonding technology. 9. DFP (dual flat package) dual flat package. It is another name for SOP (see SOP). There used to be this term, but it is basically not used anymore.
10. DIC (dual in-line ceramic package)
Another name for ceramic DIP (including glass seal) (see DIP).
11. DIL ( dual in-line)
Another name for DIP (see DIP). European semiconductor manufacturers often use this name.
12. DIP (dual in-line package)
Dual in-line package. One of the plug-in packages, the pins are drawn from both sides of the package, and the package materials are plastic and ceramic. DIP is the most popular plug-in package, and its application range includes standard logic ICs, memory LSIs, and microcomputer circuits. The pin center distance is 2.54mm, and the number of pins is from 6 to 64. The package width is usually 15.2mm. Some packages with a width of 7.52mm and 10.16mm are called skinny DIP and slim DIP (narrow DIP) respectively. But in most cases, no distinction is made, and they are simply collectively referred to as DIP. In addition, ceramic DIP sealed with low-melting glass is also called cerdip (see cerdip).
13. DSO (dual small out-lint)
Dual small out-lint package. Another name for SOP (see SOP). Some semiconductor manufacturers use this name.
14. DICP (dual tape carrier package)
Dual tape carrier package. One of TCP (carrying package). The pins are made on the insulating tape and lead out from both sides of the package. Due to the use of TAB (Automatic On-Load Soldering) technology, the package outline is very thin. It is often used in LCD driver LSI, but most of them are customized products. In addition, the 0.5mm thick memory LSI book package is in the development stage. In Japan, in accordance with the EIAJ (Electronic Machinery Industry of Japan) Association standards, DICP is named DTP.
15. DIP (dual tape carrier package)
Same as above. The Japanese Electronic Machinery Industry Association standard names DTCP (see DTCP).
16. FP (flat package)
Flat package. One of surface mount packages. Another name for QFP or SOP (see QFP and SOP). Some semiconductor manufacturers use this name.
17. Flip-chip
Flip-chip welding. One of the bare chip packaging technologies is to make metal bumps in the electrode area of the LSI chip, and then connect the metal bumps with the electrode area on the printed circuit board. The footprint of the package is basically the same as the chip size. It is the smallest and thinnest of all packaging technologies. However, if the thermal expansion coefficient of the substrate is different from that of the LSI chip, a reaction will occur at the joint, which will affect the reliability of the connection. Therefore, it is necessary to use resin to reinforce the LSI chip, and use a substrate material with substantially the same thermal expansion coefficient.
18. FQFP (fine pitch quad flat package)
Small pin center distance QFP. Usually refers to the QFP with a lead center distance less than 0.65mm (see QFP). Some conductor manufacturers use this name.
19. CPAC (globe top pad array carrier)
The American Motorola company's nickname for BGA (see BGA).
20. CQFP (quad fiat package with guard ring)
Four-side pin flat package with guard ring. One of the plastic QFPs, the pins are masked with a resin protection ring to prevent bending and deformation. Before assembling the LSI on the printed circuit board, cut the lead from the guard ring and make it into a seagull wing shape (L shape). This kind of package has been mass-produced by Motorola Company in the United States. The pin center distance is 0.5mm, and the number of pins is about 208 at most.
21. H-(with heat sink)
means a mark with a heat sink. For example, HSOP means SOP with heat sink.
22. pin grid array (surface mount type)
Surface mount PGA. Usually PGA is a plug-in package with a pin length of about 3.4mm. The surface mount PGA has display-like pins on the bottom surface of the package, and its length ranges from 1.5mm to 2.0mm. Mounting uses the method of butt welding with the printed circuit board, so it is also called butt welding PGA. Because the pin center distance is only 1.27mm, which is half smaller than the plug-in type PGA, the package body can be made not so large, and the number of pins is more than that of the plug-in type (250～528), which is a package for large-scale logic LSIs. . The encapsulated substrates include multilayer ceramic substrates and glass epoxy resin printing bases. The packaging of multilayer ceramic substrates has been put into practical use.
23. JLCC (J-leaded chip carrier)
J-leaded chip carrier. Another name for CLCC with window and ceramic QFJ with window (see CLCC and QFJ). The name adopted by some semiconductor manufacturers.
24. LCC (Leadless chip carrier)
Leadless chip carrier. Refers to a surface-mount package in which the four sides of the ceramic substrate are only in contact with electrodes without leads. It is a package for high-speed and high-frequency IC, also called ceramic QFN or QFN-C (see QFN).
25. LGA (land grid array)
Contact display package. That is, a package with array state electrode contacts is made on the bottom surface. Just plug in the socket when assembling. There are now practical ceramic LGAs with 227 contacts (1.27mm center distance) and 447 contacts (2.54mm center distance), which are used in high-speed logic LSI circuits.
Compared with QFP, LGA can accommodate more input and output pins in a smaller package. In addition, since the impedance of the lead is small, it is very suitable for high-speed LSI. However, due to the complex production and high cost of sockets, they are basically not used much. It is expected that its demand will increase in the future.
26. LOC (lead on chip)
Lead on chip package. One of the LSI packaging technologies is a structure in which the front end of the lead frame is above the chip, and bump solder joints are made near the center of the chip, and wire stitching is used for electrical connection. Compared with the original structure in which the lead frame is arranged near the side of the chip, the chip contained in the same size package has a width of about 1 mm.
27. LQFP (low profile quad flat package)
Thin QFP. Refers to the QFP with a package body thickness of 1.4mm, which is the name used by the Japanese Electronic Machinery Industry in accordance with the new QFP outline specifications formulated.
28. L-QUAD
One of ceramic QFP. Aluminum nitride used for packaging substrates has a thermal conductivity 7-8 times higher than that of aluminum oxide, and has better heat dissipation. The frame of the package is aluminum oxide, and the chip is sealed by potting, thereby suppressing the cost. It is a package developed for logic LSI, which can tolerate W3 power under natural air cooling conditions. 208-pin (0.5mm center distance) and 160-pin (0.65mm center distance) LSI logic packages have been developed, and mass production began in October 1993.
29. MCM (multi-chip module)
Multi-chip module. A package in which multiple semiconductor bare chips are assembled on a wiring substrate. According to the substrate material, it can be divided into three categories: MCM-L, MCM-C and MCM-D.
MCM-L is a component that uses the usual glass epoxy multilayer printed circuit board. The wiring density is not very high and the cost is low. MCM-C uses thick film technology to form multilayer wiring, and uses ceramic (alumina or glass ceramic) as a substrate component, which is similar to a thick film hybrid IC using a multilayer ceramic substrate. There is no obvious difference between the two. The wiring density is higher than MCM-L.
MCM-D is the use of thin film technology to form multilayer wiring, with ceramic (aluminum oxide or aluminum nitride) or Si. Al as the substrate component. The wiring scheme is the highest among the three components, but the cost is also high.
30. MFP (mini flat package)
Small flat package. Another name for plastic SOP or SSOP (see SOP and SSOP). The name adopted by some semiconductor manufacturers.
31. MQFP (metric quad flat package)
A classification of QFP in accordance with JEDEC (United Electronic Equipment Council) standards. Refers to the standard QFP with a lead center distance of 0.65mm and a body thickness of 3.8mm～2.0mm (see QFP).
32. MQUAD (metal quad)
A QFP package developed by Olin Company in the United States. Both the base plate and the cover are made of aluminum and sealed with an adhesive. Under natural air cooling conditions, power of 2.5W～2.8W can be tolerated. Japan's Shinko Electric Industry Co., Ltd. obtained a license in 1993 to start production.
33. MSP (mini square package)
Another name for QFI (see QFI), which is often called MSP in the early stages of development. QFI is the name prescribed by the Japan Electronic Machinery Industry Association.
34. OPMAC (over molded pad array carrier)
Molded resin sealing bump display carrier. The name adopted by American Motorola Company for molded resin sealing BGA (see
BGA).
35. P－(plastic)
The symbol for plastic packaging. For example, PDIP means plastic DIP.
36. PAC (pad array carrier)
Bump display carrier, another name for BGA (see BGA).
37. PCLP (printed circuit board leadless package)
Printed circuit board leadless package. The name adopted by Fujitsu for plastic QFN (plastic LCC) (see QFN). There are two sizes of pin center distance: 0.55mm and 0.4mm. It is in the development stage.
38. PFPF (plastic flat package)
Plastic flat package. Another name for plastic QFP (see QFP). The name adopted by some LSI manufacturers.
39. PGA (pin grid array)
Display pin package. One of the plug-in packages, the vertical pins on the bottom surface are arranged in an array. The packaging substrates are basically multilayer ceramic substrates. In the case where the material name is not specifically indicated, most of them are ceramic PGA, which is used in high-speed large-scale logic LSI circuits. The cost is higher. The center distance between pins is usually 2.54mm, and the number of pins ranges from 64 to 447. In order to reduce costs, the packaging substrate can be replaced by a glass epoxy printed substrate. There are also plastic PGAs with 64 to 256 pins. In addition, there is also a short-pin surface-mount PGA (butt-welded PGA) with a pin center distance of 1.27mm. (See surface mount PGA).
40. piggy back
Piggyback package. Refers to the ceramic package with socket, the shape is similar to DIP. QFP. QFN. It is used to verify the operation of the evaluation program when developing equipment with a microcomputer. For example, plug the EPROM into the socket for debugging. This kind of package is basically a customized product, and it is not circulated in the market.
41. PLCC (plastic leaded chip carrier)
Plastic leaded chip carrier. One of surface mount packages. The pins are led out from the four sides of the package and are T-shaped and are made of plastic. Texas Instruments in the United States first adopted 64k-bit DRAM and 256kDRAM, and has been widely used in logic LSI. DLD (or process logic device) and other circuits. The pin center distance is 1.27mm, and the number of pins ranges from 18 to 84. J-shaped pins are not easy to deform and easier to operate than QFP, but the visual inspection after soldering is more difficult.
PLCC is similar to LCC (also known as QFN). In the past, the only difference between the two was that the former used plastics and the latter used ceramics. But there has been a J-shaped lead package made of ceramics and a leadless package made of plastic (marked as plastic LCC. PCLP. P-LCC, etc.), which can no longer be distinguished. For this reason, the Japanese Electronic Machinery Industry Association decided in 1988 to call the package with J-shaped pins drawn from four sides as QFJ, and the package with electrode bumps on four sides as QFN (see QFJ and QFN).
42. P-LCC (plastic teadless chip carrier) (plastic leaded chip currier)
Sometimes it is another name for plastic QFJ, sometimes it is another name for QFN (plastic LCC) ( See QFJ and QFN). Some LSI manufacturers use PLCC for leaded package, and P-LCC for leadless package to show the difference.
43. QFH (quad flat high package)
Four-side pin thick flat package. A type of plastic QFP. In order to prevent the package body from breaking, the QFP body is made thicker (see QFP). The name adopted by some semiconductor manufacturers.
44. QFI (quad flat I-leaded packgac)
Quad flat I-leaded packgac. One of surface mount packages. The pins are led out from the four sides of the package and form an I-shape downwards.
Also known as MSP (see MSP). The mounting and the printed circuit board are connected by butt soldering. Since the pins have no protruding parts, the mounting area is smaller than QFP.
Hitachi Manufacturing Co., Ltd. developed and used this package for video analog ICs. In addition, Japan's Motorola Company's PLL IC also uses this package. The pin center distance is 1.27mm, and the number of pins ranges from 18 to 68.
45. QFJ (quad flat J-leaded package)
Four-side J-lead flat package. One of surface mount packages. The pins are led out from the four sides of the package and form a J-shape downwards. It is the name prescribed by the Japan Electronic Machinery Industry Association. The pin center distance is 1.27mm. There are two kinds of materials: plastic and ceramic. Plastic QFJ is called PLCC in most cases (see PLCC), which is used for microcomputer, door display, DRAM, ASSP, OTP and other circuits. The number of pins ranges from 18 to 84.
Ceramic QFJ is also called CLCC. JLCC (see CLCC). Packages with windows are used for ultraviolet erasable EPROM and microcomputer chip circuits with EPROM. The number of pins ranges from 32 to 84.
46. QFN (quad flat non-leaded package)
Quad flat non-leaded package. One of surface mount packages. Mostly called LCC. QFN is the name prescribed by the Japan Electronic Machinery Industry Association. The four sides of the package are equipped with electrode contacts. Because there are no leads, the mounting area is smaller than QFP and the height is lower than QFP. However, when stress is generated between the printed circuit board and the package, it cannot be relieved at the electrode contact. Therefore, it is difficult to make electrode contacts as many QFP pins, generally from 14 to 100. There are two kinds of materials: ceramic and plastic. When there is an LCC mark, it is basically ceramic QFN. The electrode contact center distance is 1.27mm. Plastic QFN is a low-cost package of glass epoxy printed substrate substrate. In addition to 1.27mm, there are two types of electrode contact center distance: 0.65mm and 0.5mm. This kind of package is also called plastic LCC. PCLC. P-LCC and so on.
47. QFP (quad flat package)
Quad flat package. One of the surface mount packages, the pins are led out from four sides in a seagull wing (L) shape. There are three kinds of substrates: ceramic, metal and plastic. In terms of quantity, plastic packaging accounts for the vast majority. When the material is not specifically indicated, it is plastic QFP in most cases. Plastic QFP is the most popular multi-pin LSI package. Not only used in digital logic LSI circuits such as microprocessors and gate displays, but also used in analog LSI circuits such as VTR signal processing and audio signal processing. The pin center distance has various specifications such as 1.0mm. 0.8mm. 0.65mm. 0.5mm. 0.4mm. 0.3mm. The maximum number of pins in the 0.65mm center distance specification is 304.
Japan calls QFP with a lead center distance less than 0.65mm as QFP (FP). However, the Japanese Electronic Machinery Industry will re-evaluate the form factor of QFP
. There is no difference in the lead center distance, but according to the thickness of the package body, it is divided into QFP (2.0mm～3.6mm thick). LQFP (1.4mm thick) and TQFP (1.0mm thick). .
In addition, some LSI manufacturers refer to QFP with a pin center distance of 0.5mm as shrink QFP or SQFP. VQFP. However, some manufacturers refer to QFPs with a pin center distance of 0.65mm and 0.4mm as SQFP, which makes the name somewhat confusing. The disadvantage of QFP is that when the lead center distance is less than 0.65mm, the lead is easy to bend. In order to prevent pin deformation, several improved QFP varieties have appeared. For example, the four corners of the package have a BQFP with tree finger cushions (see BQFP); a GQFP with a resin protection ring covering the front end of the pin (see GQFP); set test bumps in the package body. Place it on the pin to prevent pin deformation TPQFP (see TPQFP) that can be tested in a dedicated fixture.
In terms of logic LSI, many developed and highly reliable products are encapsulated in multilayer ceramic QFP. The minimum pin center distance is 0.4mm. Products with a pin count of up to 348 have also come out. In addition, there is also a glass-sealed ceramic QFP (see Gerqad).
48. QFP (FP) (QFP fine pitch)
Small center distance QFP. The name specified in the standards of the Japan Electronic Machinery Industry Association. Refers to the QFP (see QFP) with a lead center distance of 0.55mm, 0.4mm, 0.3mm, etc. less than 0.65mm.
49. QIC (quad in-line ceramic package)
Another name for ceramic QFP. The name adopted by some semiconductor manufacturers (see QFP. Cerquad).
50. QIP (quad in-line plastic package)
Another name for plastic QFP. The name adopted by some semiconductor manufacturers (see QFP).
51. QTCP (quad tape carrier package)
Four-side pin tape carrier package. One of the TCP packages. Leads are formed on the insulating tape and lead out from the four sides of the package. It is a thin package using TAB technology (see TAB. TCP).
52. QTP (quad tape carrier package)
Four-side pin tape carrier package. The name used by the Japan Electromechanical Industry Association for the external specifications of QTCP in April 1993 (see TCP).
53. QUIL (quad in-line)
Another name for QUIP (see QUIP).
54. QUIP (quad in-line package)
Four-row pin in-line package. The pins are led out from the two sides of the package, and every other one is staggered and bent downward into four rows. The lead center distance is 1.27mm. When the printed circuit board is inserted, the insertion center distance becomes 2.5mm. Therefore, it can be used for standard printed circuit boards. It is a package smaller than the standard DIP. NEC uses various packages in microcomputer chips such as desktop computers and home appliances. There are two kinds of materials: ceramic and plastic. The number of pins is 64.
55. SDIP (shrink dual in-line package)
Shrink DIP. One of the plug-in packages, the shape is the same as the DIP, but the pin center distance (1.778mm) is smaller than the DIP (2.54mm), so it is called this. The number of pins ranges from 14 to 90. There is also called SH-DIP. There are two kinds of materials: ceramic and plastic.
56. SH-DIP (shrink dual in-line package)
Same as SDIP. The name adopted by some semiconductor manufacturers.
57. SIL (single in-line)
Another name for SIP (see SIP). European semiconductor manufacturers often use the name SIL.
58. SIMM (single in-line memory module)
Single in-line memory module. A memory assembly with electrodes only near one side of the printed circuit board. Usually refers to the component that plugs into the socket. The standard SIMM has two specifications of 30 electrodes with a center distance of 2.54mm and 72 electrodes with a center distance of 1.27mm.
SIMM with SOJ encapsulated 1 Mbit and 4 Mbit DRAM installed on one or both sides of a printed circuit board has been widely used in personal computers, workstations and other equipment. At least 30-40% of DRAM is assembled in SIMM.
59. SIP (single in-line package)
Single in-line package. The pins are led out from one side of the package and arranged in a straight line. When assembled on a printed circuit board, the package is side-standing. The pin center distance is usually 2.54mm, and the number of pins ranges from 2 to 23. Most of them are customized products. The shape of the package varies. Some packages with the same shape as ZIP are called SIP.
60. SK-DIP (skinny dual in-line package)
A kind of DIP. Refers to a narrow DIP with a width of 7.62mm and a pin center distance of 2.54mm. Usually collectively referred to as DIP (see DIP).
61. SL-DIP (slim dual in-line package)
A kind of DIP. Refers to a narrow DIP with a width of 10.16mm and a pin center distance of 2.54mm. Usually collectively referred to as DIP.
62. SMD (surface mount devices)
Surface mount devices. Occasionally, some semiconductor manufacturers classify SOP as SMD (see SOP).
63. SO (small out-line)
Another name for SOP. Many semiconductor manufacturers in the world have adopted this nickname. (See SOP).
64. SOI (small out-line I-leaded package)
Small out-line I-leaded package. One of surface mount packages. The leads lead out from both sides of the package and form an I-shape downwards, with a center distance of 1.27mm. The mounting area is smaller than SOP. Hitachi has adopted this package in an analog IC (IC for motor drive). The number of pins is 26.
65. SOIC (small out-line integrated circuit)
Another name for SOP (see SOP). Many foreign semiconductor manufacturers adopt this name.
66. SOJ (Small Out-Line J-Leaded Package)
J-shaped pin small outline package. One of surface mount packages. The pins lead out from both sides of the package and form a J-shape downwards, hence the name. Usually plastic products, mostly used in memory LSI circuits such as DRAM and SRAM, but most of them are DRAM. Many DRAM devices packaged in SOJ are mounted on the SIMM. The pin center distance is 1.27mm, and the number of pins ranges from 20 to 40 (see SIMM).
67. SQL (Small Out-Line L-leaded package)
The name used for SOP according to JEDEC (Joint Electronic Equipment Engineering Council) standards (see SOP).
68. SONF (Small Out-Line Non-Fin)
SOP without heat sink. Same as the usual SOP. In order to express the difference of no heat sink in the power IC package, the NF (non-fin) mark is deliberately added. The name adopted by some semiconductor manufacturers (see SOP).
69. SOP (small Out-Line package)
Small outline package. One of the surface mount packages, the pins are led out from both sides of the package in a seagull wing shape (L shape). There are two kinds of materials: plastic and ceramic. Also called SOL and DFP. In addition to being used for memory LSIs, SOPs are also widely used in circuits such as ASSPs that are not too large. In the field where the input and output terminals do not exceed 10-40, SOP is the most popular surface mount package. The pin center distance is 1.27mm, and the number of pins ranges from 8 to 44. In addition, SOPs with pin center distance less than 1.27mm are also called SSOP; SOPs with assembly height less than 1.27mm are also called TSOP (see SSOP. TSOP). There is also an SOP with a heat sink.
70. SOW (Small Outline Package (Wide-Type))
Wide-body SOP, the name adopted by some semiconductor manufacturers.